Control circuit employing digital techniques for loads such as balance wheel motors

ABSTRACT

A circuit for supplying current pulses to a load which, for example, may be the coil of balance wheel motor, in response to selected control pulses derived from said coil and for inhibiting the supply of said current pulses in response to other pulses derived from said coil, where said other pulses include at least two closely spaced pulses and occur during the time interval between said selected control pulses.

United States Patent [1 1 Eaton, Jr.

[111 3,787,715 Jan. 22, 1974 [54] CONTROL CIRCUIT EMPLOYING DIGITAL 3,553,957 l/l97l Dome et a1. 58/23 TECHNIQUES FOR LOADS H AS 3,564,838 2/ 1971 Fellrath et a1. 58/23 A 3,608,301 9/1971 Loewengart 58/23 A BALANCE WHEEL MOTORS 3,737,746 6/1973 Cielaszyk et al 318/130 [75] Inventor: Sargent Sheffield Eaton, Jr.,

warren, Primary ExaminerDonovan F. Duggan [73] Assignee: RCA Corporation, New York, NY. g g Agentlor Christofferson; Henry c anzer [22] Filed: I Aug. 30, 1972 [21 Appl. No.: 284,907 I [57] ABSTRACT Y Y A circuit for supplying current pulses to a load which, [52] US. Cl. 318/130, 318/132, 58/23 for example, y be the coil of? balance wheelmotor, 51 lm. Cl. H02k 33/00 in response to Selected control pulses derived from 58 Field of Search 318/122-139; said coil and for inhibitinglthe pp y of said current 58/23, 29 23 25 pulses in response to other pulses derived from said 3 coil, where said other pulses include at least two [56] References Cit d closely spaced pulses and occur during the time inter- UNITED STATES PATENTS val between said selected control pulses. 3,540,207 11/1970 Keeler 58/23 9 Claims, 7 Drawing Figures mj +l 5v CLOCK PULSES@ |28Hz MOTOR [05 COIL E CLOCKS STAGE ZERO CROSSING DETECTOR R COUNTER c c c c c PAIENIE JMMM 3.787, 715

SHEEI 1 0F 4 Fig. 1

304 COUNTERWEIGHT ZERO CROSSING DETECTOR CONTROL CIRCUIT EMPLOYING DIGITAL TECHNIQUES FOR LOADS SUCH AS BALANCE WHEEL MOTORS BACKGROUND OF T HE INVENTION The problem dealt with in this application may be, perhaps, best understood by referring to FIG. 1 which illustrates diagrammatically a balance wheel motor for a watch or a clock. FIG. 1 shows a rotating member 300 which may be part'of a circular balance wheel or which may be a plain rectangular bar which is pivoted on a shaft 301 and is free to oscillate back and forth across a stationary coil 14. The member 300 has a magnet 302 at one end and a counterweight 304 at the other end. Assume now that one end of coil 14 is'returned to a source I of operating potential (e.g., 1.5 volts) and that the other end of the coil denoted by A is connected to an oscilloscope. The member 300 initially may be set into oscillation by shaking. As the member 300 oscillates back and forth across coil 14, the pulses shown in waveform A of FIG. 3 are produced at'A and may be displayed on the scope. That is, as the member 300 travels in one direction across the coil, it induces a signal denoted as X and when it travels across the coil in the opposite direction, it induces a signal denoted as Y which is the mirror image of the X signal.

To ensure continued oscillation or reciprocating rotation, it is necessary to periodically supply pulses of current to, the coil to supply energy to the system. That is, current pulses supplied to the coil create an electromagnetic fie-ld which attracts and/or repels the magnet 302 located on member 300 therebysustaining the oscillatory motion of member 300. However, it may be desirable, for example, to supply current pulses to the coil 14 only during the presence of X signals and not during the presence of the Y signals. More generally, it may be desirable and/or necessary to perform some functions only on alternate signals (e.g., X signals) while inhibiting the performance of these functions when the remaining signals (e.g., Y signals) occur. This gives rise to the problem of sensing the desired signals and rejecting the others.

In known prior art circuits, sensing of the desired signals was done by attempting to compare differences in amplitude. It should also be mentioned that in the prior art a level detector was used to sense the transition of the signals.

A level detector generally, and as used herein, refers to a circuit which senses when an input signal exceeds a given bias level and which produces an output manifesting such occurrence.

' A level detector may be used to digitize a signal. That is, it may be used to generate binary pulses in response to signals exceeding the bias level. But, in the known prior art circuits the level detector was biased to discriminate in amplitude between the desired and undesired pulses. This has disadvantages as discussed below.

For example, assume that a function is to be performed when the X signal goes negative and that therefore the X signals are to be sensed. However, the Y signal also has negative going excursions. As illustrated in waveform A the Y signals go down to L3 volts and the X signals go down to 1.1 volts. Therefore, before the system can detect the presence of an X signal, the X signal has to exceed 1.3 volts in the negative going direction. Obviously, by the time the X signal exceeds 1.3

volts, a considerable portion of the X signal width is lost. Therefore the time available to perform the desired and/or necessary function is considerably decreased and may be insufficient. Secondly, the prior art system requires a relatively accurate and reliable comparator. Such a comparator, which for a mass produced item such as watches would have to have extremely low power dissipation and also be small, reliable and cheap, connot at this point in time be reliably and economically mass produced.

Therefore, the prior art system, relying on analog techniques for sensing the presence of desired signals is unsatisfactory.

SUMMARY OF THE INVENTION The invention resides in part in the recognition that first and second signals such as the X and Y signals, are transformed into first and second sets of pulses having different patterns. One set of pulses comprises a single pulse and the other set of pulses comprises at least two relatively Closely spaced pulses. The two sets alternate having a relatively fixed period. The invention also resides in means for sensing said first and second pulse patterns and for supplying Current pulses of first polarity to a load in response to pulses from saif first set of pulses, and for either inhibiting the supply of current to said load or for supplying curren pulses to said load of second polarity opposite to that of said first polarity in response to puses from said second set of pulses. The invention thus resides inpart in discriminating between teh two sets of pulses on the basisof the difference in their patterns rather than on the difference in signal amplitude.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a diagrammatic representation of a balance wheel watch motor;

FIG. 2 is a schematic diagram of a circuit embodying the invention;

FIGS. 3A and 3B are waveforms of various signals and pulses associated with the circuit of FIG. 2;

FIG. 4 is a schematic diagram of a zero crossing detector which may be used in the circuit of FIG. 2; and

FIGS. 5A and 5B illustrate different circuit arrangements for supplying current pulses to the coil 14 of FIGS. l and 2.

DETAILED DESCRIPTION OF THE INVENTION In the circuit of FIG. 2 the load 15 includes a coil 14 which may be the coil 14 of the balance'wheel of FIG. 1. The coil 14 is connected between terminal 12 and node 3. The source-drain path of an N conductivity type switching transistor 38 is connected between node 3 and ground potential. With the balance wheel (not shown) rotating and with transistor 38 non-conducting, there is produced at node 3 the waveshape A shown in FIG. 3A. An operating potential which in this embodiment is nominally 1.5 volts is applied to terminal 12.

Node 3 is alternating current (-AC) coupled by means of capacitor C1 to zero crossing detector network 16.

Network 16 is of the type which produces a positive going output pulse whenever the (A) signals applied to its input crosses the 1.5 volt bias level going in a negative direction.

The term zero crossing detector as used herein may refer to a detector which senses a signal crossing zero volts or crossing a fixed direct current (DC) voltage level. For example, whenever the input signals at A go negative with respect to the fixed level of 1.5 volts DC, the zero crossing detector 16 senses the negative going crossings and produces the pulses shown in waveform B of FIG. 2. The zero crossing detector 16 may be any one of a number of known circuits adapted to perform this function. One such circuit is shown in FIG. 4. The circuit of P16. 4 includes an amplifier l1 comprised of P-conductivity t'yp'e transistor T1 having its conduction path connected in series with N-type transistor T2 between +1.5 volts and ground. A biasing resistor R1 is connected between 1.5 volts and the gate electrodes of transistors T1 and T2, and a feedback resistor R2 is connected between the gate electrodes and the drain electrodes of transistors T1 and T2. The output of amplifier 11 is then fed to two cascaded inverters to produce pulses of desired polarity at B. The values of R1 and R2 may be chosen so that with no AC signal at A the level at the output of amplifier I1 is low producing a signal level at B of zero volts.

In response to the X and Y signals shown in Waveshape A the network 16 produces two sets or groups of pulses as shown in waveshape B of FIG. 3A. The first set includes single positive going 20 millisecond wide pulses (13, 13a) occuring at intervals of approximately 250 milliseconds. The second set includes two relatively closely spaced positive going millisecond wide pulses (11, 12, 11a, 12a). The pair (11, 12) of pulses occur approximately 20 milliseconds apart and alternate with pulses from the first set. The output B of detector 16 is connected to the reset (R2) input of flip flop No. 2 (FF2) and to the first input (1) of AND gates 34 and 26.

Flip Flop No. 2 (FF2) and flip flop No. 1 (FFI) are set reset flip flops, each flip flop having set input (S), a reset input (R), and output (Q) and a complementary output (6). A high level signal (e.g., volts) denoted as a logic 1 applied to the R input causes Q to go low (logic lT) andO to go high (logic 1 A high level signal applied to the S input causes 0 to go high and Q to go low. The 02 output of FF2 is applied to the reset input (R) of a 5 stage counter 18, to the set input (S1) of PH and to the reset input (R3) of flip flop 3 (FF3).

The counter 18 has a clock input terminal 105 to which clock pulses are applied. The clock pulses supplied to the counter have a frequency of 128 HZ. This is equivalent to 1 cycle every 7.8 milliseconds and every count of the counter is thus equal to 7.8 milliseconds. In the description to follow, it will sometimes be assumed for ease of explanation that each cycle is 8 milliseconds long. The counter is triggered (counts) on a negative going clock edge. The counter may be reset by the application of a high level at its R input which causes C1, C2, C3, C4, and C5 to be reset to zero. The C3 output (2 binary position) of counter 18 is connected to inverter 20 which produces C3 at its output. The C4 output (2 binary position) of counter 18 is connected to the first input (1) of AND gate 31 which functions to decode the count of 24 and to the clock input (CL) of FF3. The C5 output (2 binary position) of counter 18 is connected 1 0 the second input (2) of AND gate 31. The output of AND gate 31 which when high indicates the presence of the count of 24 in the counter 18 is applied to the second set input (S2) of FF2.

the output of inverter 20 (C3) is applied to the first input (1) of NOR gate 25 and the 03 output of FF3 is applied to the second input (2) of NOR gate 25. The output D of NOR gate 25 is applied to the second input (2) of AND gate 26 and NOR gate 30, respectively. The output of AND gate 26 is applied to the R1 i put of FF]. and the output (l()of NOR gate 30 is app ied to the first set input (S21) of FF2.

Flip flop No. 3 (FF3) is a clocked flip flop which trig gers on a positive going clock edge. The 03 output of FF3 is fed back to its D3 input and is applied to the segond input (2) of 0, gate 34. FF3 is reset (Q3 0. Q3 1) when the input to R is high. Due to the feedback from O3 to its D3 input FF3 changes state whenever a positive going signal is applied to its clock input.

The third input (3) of AND gate 34 is connected to terminal 36 to which is applied the motor pulses of the type shown in FIG. 3B. The motor pulses have a repetition rate of approximately 500 pulses per second. One half of the motor pulses are high (1.5 volts) for onefourth of their period and the other half of the motor pulses are high (1.5 volts) for three-fourths of their period. This particular arrangement of pulses optimizes the frequency stability of the motor. However, symmetrical pulses as well as pulses having different ratios of high to low could also be used.

The output of gate 34 denoted E is connected to the gate elgctrode of transistor 38. When gate 34 is enabled (B Q3 l) the pulses present at node 36 are passed to output E. In response to the pulses produced at E, transistor 38 is turned on and off. The motor pulses turning transistor 38 on and off produce signals at A of the type shown in waveform A of HG. 3B. This last waveform is somewhat idealized in that it does not include the switching transients which occur on the leading and trailing edges of the pulses.

Where transistor 38 is turned on (E l) a current pulse is supplied to the coil. That is, current now flows from terminal 12 through the coil and through the source-drain path of the transistor to ground. When transistor 38 is turned off (E 0) the coil is disconnected from the ground return.

ln'the description of the operation which follows, it is assumed that the circuit starts from a rest position and that the first cycle sensed by the circuit includes a pulse 11 closely followed by pulse 12 and eventually followed by a pulse 13.

The operation of the circuit of FIG. 2 may best be explained by referring to the waveform shown in F IG. 3. Also, in the discussion to follow a high voltage level 15 volts) will be referred to as a high, a logic 1 or 1 and a low voltage level 0 volts) will be referred to as a logic 0 or low or 0.

Assume first that at time t a Y type signal is generated at node 3 causing relatively closely spaced pulses 11 and 12 to be generated at the output of detector 16 as shown in waveform B. Typically, the amplitude of pulses 11 and 12 is l.5 volts and their pulse width is 10 milliseconds and the elapsed time between the falling edge of pulse 10 and the rising edge of pulse 12 is 20 milliseconds.

The positive going pulse 11 is applied to the reset input (R2) of FF2 and to the first inputs (1) of AND gates 26 and 34. Pulse 11 causes the Q2 output of F F2 to go low (02 0). When 02 is low the reset signal is removed from counter 18, enabling the counter to count the clock pulses applied to terminal 105. 02 low also removes the reset signal from R3 of FF3.

Starting with time t the pulse 11 at B and the 63 level appliedto inputsland 2, respectively, of AND gate 34 are high B Q3 1). Therefore, the motor pulses applied to terminal 36 are passed to output E of gate 34 causing transistor 38 to go on and off for as long (a period of milliseconds) as pulse 11 is present. As described below only onv the first cycle are motor pulses produced at E during an 11 or 12 pulse. Once the circuit has locked in on thepulses denoted 13, no motor pulses are passed to output E during the occurence of subsequent pulse 11 or 12 derived from the Y signals.

From time t, to time t the signal at B is low and E remains low. At time t: which, as shown in waveform B, occurs approximately 30 milliseconds after t pulse 12 goes high. This has no effect on F1 2 which was reset by pulse 11 but applied a 1 to the first inputs of AND gates 26 and 34. At time t, which occurs approximately 31.2 millisecond after t a fourth (12.8 HZ).clock pulse is applied to counter 18 and the C3 output of counter 18 goes high. (The count of 4, in binary terms, is 00100 where l is in the C3 position). When C3 goes high, the output oiinverter 20 (C3) goes low (63 0). Thus at time t, C3 and Q3 which are the two inputs to NOR gate are low causing the output D of NOR gate 25 to go high. At time 2 when D goes high, the two inputs to AND gate 26 are'high (B D l) and the gate supplies a high to the R1 input of FFl causing O1 to go low. Thus FFl is reset, that is, 01 goes from .1 to 0 when two relatively closely spaced pulses (11, 12) are produced at B. At this time NOR gate 30 remains in its previous condition, that is, K 0 since one of its inputs D is 1 while its other input O1 is 0. At time t, (approximately 40 milliseconds after time t the pulse 12 returns to 0 (B 0) which disables AND gates 26 and 34. Note that FFl remains reset with O1 0.

During the first cycle, that is, the first time pulses 11 and 12 gzcur prior to the occurrence of a pulse 13, the B and'Q3 inputs to gate 34 are high and motor pulses are passed to output E and applied to the gate electrode of transistor 38. However, after the occurrence of a pulse 13, motor pulses are inhibited from being passed to output E during the presence of subsequent pulses 11 and 12.

At time t. approximately 62.4 milliseconds after time t the counter reaches the count of 8 and the C4 output goes high and the C3 output goes low. The count of 8, in binary terms, is 01000 where l is the C4 position. C3 changes to a 1 and D changes to 0. The two inputs to NOR gate 30 (D Q1 0) now are both 0 so that K changes to a 1. K 1 applied to the set side (S1) of FF2 causes 02 to go high (02 1). Q2 high resets counter 18 to the count of zero (C1 C2 C3 C4 C5 0), resets F F3 causing 63 to go high and O3 to go low and sets FFl causing O1 to go high which in turn causes K to return to zero. The circuit has thus been reset to the conditions existing just prior to time t it should be appreciated at this point that the circuit sensed the presence of relatively closely spaced pulses l1 and 12 and prepared the circuit for the next succeeding pulse 13. That is, at time t, B is high (because ofclosely spaced pulse 12) when D is high. in response to B D 1 the FFl is reset with O1 going to 0. Then at time t, with 01 still at 0, D changes from 1 to 0 and a set pulse is applied to FFZ which resets the counter and restores the circuit to its initial conditions. This enables the next succeeding pulse 13 to initiate a new cycle At time i (approximately 135 milliseconds after t and milliseconds after time 1 a pulse 13 corresponding to an X signal is produced at B and current pulses are to be applied to the motor coil 14.

At time t ()3 is high and since B is high, the motor pulses applied to terminal 36 pass through AND gate 34. The output E is applied to the gate electrode of transistor 38 causing current pulses to flow through the coil 14 at the desired time in the desired direction. These pulses are passed from time I until time when pulse 13 returns to zero disabling AND gate 34. At time t, concurrently with the above, the leading edge of pulse 13 resets FF2 and causes O2 to go low. With Q2 0 counter 18 begins counting as explained above.

At time 1 (31.2 milliseconds after time t, corresponding to'the count of 4 and approximately 1 1.2 milliset o nds after the return of pulse 13 to 0), C3 goes high, C3 goes low and D changes to 1. But now when D goes to l, B is 0 (since time t and AND gate 26 remains disabled and FFl remains set with O1 1.

At time t which occurs 62.4 milliseconds after time t5, C3 changes from 1 to 0 and C4 changes from 0 to 1. The count has gone from 7 (00111) to 8 (01000). The change of C3 to 0 causes D to go from 1 to 0 but the change in D now has no effect on any part of the circuit. The change in C4 from 0 to 1 triggers FF3 and causes O3 to go to 1 and 63 to go to 0. The O3 0 applied to gate 34 disables it and motor pulses can not pass to output E.

At time r and t (approximately and milliseconds, respectively after time t pulses 1 1a and 12a occur but these pulses now have no effect on the circuit and are effectively blanked out. The high at B produced by pulses 110 and/or 12a is applied to FF2 but it has no effect since FF2 is already reset (Q2 0) and the output of gate 3 4 is maintained at E 32 0 since the gate is disabled by Q3 is 0. It is important to note that in response to a single pulse 13 succeeding pulses-11 and 12 are prevented from in any way affecting the circuit. Only pulses of similar type to pulse 13 and occurring with approximately the same periodicity as pulse 13 will cause motor pulses and current pulses to be supplied to the coil.

At time 1,, counter 18 reaches the count of 24, in binary terms 11000, with C5 and C4 both 1. Time 1, occurs 187.2 milliseconds after time t, and 1, is approximately 50 milliseconds after thefalling edge of pulse 12a. At time 1,, AND gate 31 which in effect is a decoder of the 24 count produces a 1 which is applied to the S2 input of F F2. The 1 applied to S2 of FFZ sets the flip flop causing O2 to go to 1. The high signal on Q2 resets counter 18 and FF3 and maintains FFl s e t Therefore, C 1 through C5 go to zero, Q3 goes to 0, Q3 goes to 1 and Q1 remains at 1.

The circuit is now in condition to receive the next positive going pulse on waveform B. The next pulse is pulse 13a and the cycle just described from time t, to time will be repeated with pulses 11 and 12 being excluded from affecting the output E.

When starting from a standstill position, the first pulse to the circuit is a pulse 12, the circuit cycles blanking the succeeding pulse 13 and then allows the next succeeding 11 and 12 type pulses following which the circuit locks in on the 13 type pulse. This is demonstrated as follows. Assume that the first pulse present at B is a pulse 12. This resets FF2 causing O2 to go low reaches the count of'8 (approximately 62.4 milliseconds after the leading edge of pulse 12). The C4 output then changes from zero to 1 gausing FF3 to change state. That is, 03 becomes 1, ()3 changes from I to 0. Since Q3 is high, D is low and will remain low until Q3 changes state. The next succeeding pulse 13 to occur, approximately 105 milliseconds after the preceding pulse 12, can not affect the circuit or the output at E. For, when the pulse 13 is applied to FF2 the latter is already in its iiset state due to thepreceding pulse 12. Also, since O3 is gate 34 is disabled and FF! is already set.

However, at the count of 24 (:187 milliseconds after the application of a first pulse 12) the C4 and C5 counter outputs go high setting FF2 which causes counter 18 to be res t to zero and FF3 to be reset such that O3 is low and Q3 is'high. The circuit is now ready to receive the next succeeding pulses 11 and 12. One cycle of these pulses as explained above pass through the circuit but the circuit locks in on the next pulse 13 succeeding the pair of pulses 11 and 12. Once the circuit is locked in on the type of pulse 13 any further pulse 11 and 12 are inhibited as described above and no longer affect the circuit.

In summary, in the operation of the circuit, the circuit senses and locks in on a desired pulse and blocks undesired pulses such as 11 and 12 which are relatively closely spaced and which occur in the interval between two desired pulses.

The AND gates shown in FIG. 2 may in practice be comprised of a NAND gate in series with an inverter. Similarly, the flip flops 1 and 2 may be comprised of two cross coupled NOR gates. It should also be evident that the circuit may be fabricated using many alternative logic arrangements without departing from the scope of the invention.

In a test circuit flip flops l and 2 as well as all the other logic gates were formed from gates bearing RCA part number TA 5987 which corresponds functionally to RCA components bearing the part number CD 4007A. The counters and flip flop No. 3 were made from parts bearing RCA part number TA 5938, TA 5939, corresponding functionally to components hearing RCA designation CD 4020A. The standard counter circuits were modified to provide an output corresponding to the count of 4. The test circuits employed complementary metal oxide semiconductor (C-MOS) devices made by the silicon gate process. This enables the manufacture of low power dissipation devices operable at very low operating potential (e.g., 1.5 volts). The silicon gate process enables the manufacture of semiconductor devices having very low threshold voltages which can therefore operate at low operating potentials.

As shown in FIG. 5A, the coil can be connected in series with a P-type transistor switch T3 such that one end of the coil is permanently connected to ground and enabling the positive side of the power supply to be periodically applied to the other end of the coil. Where the transistor is connected as shown in FIG. 5A similar operation to that described for FIG. 2 is obtained if the pulses applied to the gate electrode of transistor T3 are the inverse (E) of the pulses applied to transistor 38. In the bridge circuitof FIG. 58 pulses could be supplied to the coil during both the X and Y pulses. Tran sistors T4 and T5 would be turned on when a pulse of the type illustrated by pulse 13' is present and transistors T6 and T7 would be turned on during the time interval corresponding to the time interval between the falling edge of pulse 11 and the rising edge of pulse 12. During the presence of the X pulses current pulses would be supplied in one direction through the coil and during the presence of the Y pulses current pulses would be supplied in the opposite direction through the coil. However, this circuitmay'be somewhat inefficient because there are two transistors in series with the coil and where the operating potential is low the voltage drops across the transistors result in that much less voltage across the coil. Also, this scheme requires four transistors as opposed to the single transistor shown in FIG. 2 or in FIG. 5A.

It may also be noted that the variation of the A wave due to the superimposition thereon of the motor pulses as shown in FIG. 38 does not alter the operation of the circuit. In response to pulses of the type denoted as pulse 13 the variations at A also occur with the signal at B and at E. Also, since FF2 is reset by the leading edge of the pulse 13 any negative going pulse applied to R2 hasno effect on the flip flop.

Though the waveform A as illustrated herein result from the reciprocating rotation of a magnet over a coil, it should be evident that the invention is not limited to signals produced by these means or to exactly those signals.

Also, though the invention as illustrated herein includes means for discriminating between two groups of pulses where one group consists of a single pulse and the second group includes two pulses, it should be evident (at least when the circuit is locked in to the single pulse 13) that the second group of pulses could include more than two. closely spaced pulses.

What is claimed is:

1. The combination comprising:

a load; v

first means, coupled to said load, which when enabled supplies current pulses to said load;

a signal input terminal coupled to said load for receiving a train of pulses derived from said load having a periodic pattern of a single pulse followed by at least two relatively closely spaced pulses, and

means coupled to said signal input terminal for sensing said closely spaced pulses and for in response to the next occurring single pulse enabling said first means and said means including means responsive to said single pulse for inhibiting the closely spaced pulses from enabling said first means.

2. The combination as claimed in claim 1 further including two terminals for the application therebetween of a source of operating potential wherein said load includes a coil connected at one end to one of said two terminals and wherein said first means includes a switch connected between the other end of said coil and the other one of said two terminals.

3. The combination as claimed in claim 2 wherein a zero level detector is connected between the junction of said coil and said switch and said signal input terminal, wherein the zero level detector converts the signals generated at said junction into said periodic pattern of 5 a single pulse followed by a pair of relatively closely spaced pulses.

4. The combination as claimed in claim 2 further including means rotatably mounted adjacent to said coil; wherein the current pulses supplied to said coil sustain the oscillatory motion of said rotatably mounted means; and wherein the oscillation of said rotatably mounted means across said coil induce in said coil alternating X and Y signals where the X signal is the mirror image of the Ysignal.

5. The combination as claimed in claim 4 wherein said rotatably mounted means is part of a balance wheel and includes a magnet.

6. The combination as claimed in claim 1 wherein said means for sensing the closely spaced pulses in cludes a flip flop and a counter, wherein said counter includes means for in response to a first pulse producing a time t, after said first pulse a given binary level for a period T1; and wherein said means for sensing includes means responsive to said level and to the concurrent presence of a second pulse relatively closely spaced to said first pulse occurring during said period T1 for putting said flip flop in a condition to change in response to a subsequent pulse.

7. The combination as claimed in claim 6 wherein said subsequent pulse is a single pulse and wherein in response to said single pulse said counter generates a time after the occurrence of said single pulse a signal for inhibiting the supply of current pulses during the presence of the next occurring closely spaced pulses; and wherein a time t;, after the occurrence of said single pulse where time 2 is later than time and occurs after the occurrence of said relatively closely spaced pulses the counter is reset to zero and said flip flop is put in a condition to begin a new cycle.

8. The combination comprising:

coil;

means rotatably mounted adjacent to said coil for,

per each cycle of rotation of said means, alternately inducing first and second signals across said coil in response to a first or a second direction of rotation, respectively;

first means coupled to said coil for when enabled supplying current pulses to said coil for sustaining the oscillatory motion of said rotatably mounted means;

digitizing means coupled to said coil for sensing said first and second types of signals and for producing in response thereto first and second sets of pulses, where said first set includes a single pulse per cycle and said second set includes at least two relatively closely spaced pulses per cycle; and

second means coupled to said digitizing means for sensing said second set of pulses and for in response to the next occurring pulse from said first set enabling said first means and said second means including means responsive to said first set of pulses for inhibiting the second set of pulses from enabling said first means.

9. The combination comprising:

a coil;

means rotatably mounted adjacent to said coil for, per cycle,alternatively including first and second signals across said coil in response to a first or a second direction of rotation, respectively;

digitizing means coupled to said coil for sensing said first and second types of signals and for producing in response thereto first and second sets of pulses, where said first set includes a single pulse per cycle and said second set includes at least two relatively closely spaced pulses per cycle; and

second means coupled to said digitizing means for in response to said first set of pulses supplying current pulses of first polarity to said coil and for in response to said second set of pulses supplying current pulses to said coil of second polarity opposite to that of said first polarity, said supply of current pulses for causing the continued oscillation of said rotating means.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,787,715 Dated Januarl 22, 1974 Invent fl Sargent Sheffield Eaton. Jr

It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Col. 2, line 25 "saif should be said line- 27 "curren" should be current line 29 "puses" should be pulses line 30 "inpart" should be in part line 31 "teh" should be the line 31 "basisof: should be basis of Col. 3, line 39 "(logic 0)" should be (logic 0) Col. 4, line 2- "input" should be inputs line 10 "of 0," should be of AND line 48 "waveform" should be waveforms Col. 5, line 17, "applied" should read applies Col. 6, 1ine,38 "E 32 0" should be E 0 Col. '8, line 34 "result" should be results Claim 1, line 9 before "means" insert second line 12 after "said" insert second Claim 8, lineZ before "coil" insert a e Signed-and sealed this 6th day of August 197% (SEAL) Attestz v MCCOY M. GIBSON, JR. C. MARSHALL DANN Attesting Officer Commissioner of Patents FORM po'wso ($69) I uscoMM-Dc 60376-P69 3530 6l72 v u.s. covnuutwr rnm'rmc OFFICE Iss9 o-sse-au v UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,787,715 Dated January 22, 1974 lnventofls) Sar ent Sheffield Eaton. Jr

It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Col. 2, line 25 "saif",should be said line- 27 "curren" should be current line 29 "puses" should be pulses line 30 "inpart" should be in part line 31 "teh" should be the line '31 "basisofl should be basis of Col. 3, line. 39 "(logic 0)" should be (logic 0) Col. 4, line 2 "input" should be inputs linelO "of 0," should be of AND- line 48* "waveform" should be waveforms Col. 5, line 17, "applied" should read applies Col. 6, line v38 "E 32 0" should be E 0 Col. -8, line 34 "result" should be results Claim 1, line 9 before "means" insert second line 12 after "said" insert second Claim 8, line 2 before "coil" insert a Signed-and sealed this 6th day of August 197A.

(SEAL) McCOY M. GIBSON, JR. 7 C. MARSHALL DANN Attesting Officer Commissioner of Patents FORM PC4050 no'sg) uscoMM-oc wave-P69 3530 6l72 w uvs. covnuuim' rnnmuc ornc: no o-us-au 

1. The combination comprising: a load; first means, coupled to said load, which when enabled supplies current pulses to said load; a signal input terminal coupled to said load for receiving a train of pulses derived from said load having a periodic pattern of a single pulse followed by at least two relatively closely spaced pulses, and means coupled to said signal input terminal for sensing said closely spaced pulses and for in response to the next occurring single pulse enabling said first means and said means including means responsive to said single pulse for inhibiting the closely spaced pulses from enabling said first means.
 2. The combination as claimed in claim 1 further including two terminals for the application therebetween of a source of operating potential wherein said load includes a coil connected at one end to one of said two terminals and wherein said first means includes a switch connected between the other end of said coil and the other one of said two terminals.
 3. The combination as claimed in claim 2 wherein a zero level detector is connected between the junction of said coil and said switch and said signal input terminal, wherein the zero level detector converts the signals generated at said junction into said periodic pattern of a single pulse followed by a pair of relatively closely spaced pulses.
 4. The combination as claimed in claim 2 further including means rotatably mounted adjacent to said coil; wherein the current pulses supplied to said coil sustain the oscillatory motion of said rotatably mounted means; and wherein the oscillation of said rotatably mounted means across said coil induce in said coil alternating X and Y signals where the X signal is the mirror image of the Y signal.
 5. The combination as claimed in claim 4 wherein said rotatably mounted means is part of a balance wheel and includes a magnet.
 6. The combination as claimed in claim 1 wherein said means for sensing the closely spaced pulses includes a flip flop and a counter, wherein said counter includes means for in response to a first pulse producing a time t1 after said first pulse a given binary level for a period T1; and wherein said means for sensing includes means responsive to said level and to the concurrent presence of a second pulse relatively closely spaced to said first pulse occurring during said period T1 for putting said flip flop in a condition to change in response to a subsequent pulse.
 7. The combination as claimed in claim 6 wherein said subsequent pulse is a single pulse and wherein in response to said single pulse said counter generates a time t2 after the occurrence of said single pulse a signal for inhibiting the supply of current pulses during the presence of the next occurring closely spaced pulseS; and wherein a time t3 after the occurrence of said single pulse where time t3 is later than time t2 and occurs after the occurrence of said relatively closely spaced pulses the counter is reset to zero and said flip flop is put in a condition to begin a new cycle.
 8. The combination comprising: coil; means rotatably mounted adjacent to said coil for, per each cycle of rotation of said means, alternately inducing first and second signals across said coil in response to a first or a second direction of rotation, respectively; first means coupled to said coil for when enabled supplying current pulses to said coil for sustaining the oscillatory motion of said rotatably mounted means; digitizing means coupled to said coil for sensing said first and second types of signals and for producing in response thereto first and second sets of pulses, where said first set includes a single pulse per cycle and said second set includes at least two relatively closely spaced pulses per cycle; and second means coupled to said digitizing means for sensing said second set of pulses and for in response to the next occurring pulse from said first set enabling said first means and said second means including means responsive to said first set of pulses for inhibiting the second set of pulses from enabling said first means.
 9. The combination comprising: a coil; means rotatably mounted adjacent to said coil for, per cycle, alternatively including first and second signals across said coil in response to a first or a second direction of rotation, respectively; digitizing means coupled to said coil for sensing said first and second types of signals and for producing in response thereto first and second sets of pulses, where said first set includes a single pulse per cycle and said second set includes at least two relatively closely spaced pulses per cycle; and second means coupled to said digitizing means for in response to said first set of pulses supplying current pulses of first polarity to said coil and for in response to said second set of pulses supplying current pulses to said coil of second polarity opposite to that of said first polarity, said supply of current pulses for causing the continued oscillation of said rotating means. 